Method of forming a nonvolatile stacked memory

Details Method of forming a nonvolatile stacked memory Method of forming a nonvolatile stacked memory

1992-06-17

1994-04-26

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257318, 437 43, 437 48, H01L 29788

Patent

active

053069358

ABSTRACT:
A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

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patent: 4713142 (1987-12-01), Mitchelle et al.
Inoue et al. "A Three Dimensional Static RAM", IEEE Device Letters, vol. ED 1-7, No. 3, May, 1986, pp. 327-329.
Muller et al. "Device Electronics For Integrated Circuits "by Muller et al. John Wiley and Sons., 1986, pp. 452-454.

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