Integer and floating point register alias table within processor

Details Integer and floating point register alias table within processor Integer and floating point register alias table within processor

1993-09-30

1997-03-18

Harvey, Jack B.

G06F 1300

Patent

active

056131321

ABSTRACT:
A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources. Logic is provided for performing prioritized table reads in parallel for all uops and prioritized table writes in parallel for all ups. There is a separate integer and floating point RAT. Up to four uops may be processed by the RAT logic within a given clock cycle.

REFERENCES:
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5293500 (1994-03-01), Ishida et al.
patent: 5323489 (1994-06-01), Bird
patent: 5355457 (1974-10-01), Shebarow et al.
patent: 5371684 (1994-12-01), Iadonato et al.
Author, Mike Johnson, entitled Superscalar Microprocessor Design, Advance Micro Devices, Prentice Hall Series in Innovative Technolgoy, 1991, pp. 1-289.
Val Popescu, et al. entitled, "The Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13, 63-73.

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