Dynamic random access memory device improved in testability with

Details Dynamic random access memory device improved in testability with Dynamic random access memory device improved in testability with

1992-04-30

1993-12-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, G11C 700

Patent

active

052709825

ABSTRACT:
A dynamic random access memory device refreshes data bits stored in the memory cell array thereof, and a self-refresh controller incorporated therein is responsive to an external row address strobe signal and an external column address strobe signal controlled in one of first, second and third sequences for selectively activating component circuits provided in a data path from the bit line pairs and a data terminal, wherein the self-refresh controller only activates parts of the data path used for developing the data bits on the bit line pairs to a restore level in the autorefreshing mode so as to decrease current consumption; however, the self-refresh controller activates all of the component circuits in the data path in the diagnostic mode for carrying out a testing operation on an internal address counter.

REFERENCES:
patent: 4549284 (1985-10-01), Ikuzaki
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4870620 (1989-09-01), Yamagata et al.
patent: 4985868 (1991-01-01), Nakano et al.

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