Method of erasing data stored in electrically erasable and progr

Details Method of erasing data stored in electrically erasable and progr Method of erasing data stored in electrically erasable and progr

1994-04-05

1995-05-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 1140

Patent

active

054146658

ABSTRACT:
Data bits stored in a flash EEPROM are erased by biasing n-type source regions of floating gate type field effect transistors such that accumulated electrons are evacuated as Fowler-Nordheim tunneling current, and, the p-type semiconductor substrate, the n-type source regions and the control gate electrodes are, thereafter, biased to a negative voltage level, a first positive voltage level and a second positive voltage level for injecting hot electrons into the floating gate electrode depending upon the amount of residual electrons in each floating gate electrode, thereby self-calibrating the threshold level of the floating gate type field effect transistors.

REFERENCES:
patent: 5255237 (1993-10-01), Kodama
patent: 5295107 (1993-03-01), Okazawa et al.
S. Yamada et al., "A self-Convergence Erasing Scheme for a Simple Stacked Gate Flash Eeprom", IEDM Technical digest, 1991, pp. 307-310.

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