Method of testing an operation of a semiconductor memory device

Details Method of testing an operation of a semiconductor memory device Method of testing an operation of a semiconductor memory device

1996-01-17

1997-03-18

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365 63, 365149, G11C 700

Patent

active

056129190

ABSTRACT:
A semiconductor memory device includes a main bit line; a plurality of sub-bit line pairs provided corresponding to the main bit line pair; a plurality of transistor pairs provided respectively corresponding to the plurality of sub-bit line pairs, each transistor pair being responsive to a prescribed selection signal for connecting one sub-bit line of a corresponding sub-bit line pair to one main bit line of the main bit line pair and connecting the other sub-bit line thereof to the other main bit line thereof; a plurality of word lines; a plurality of memory cells connected to sub-bit line pairs and word lines; and a selecting circuit for selecting one transistor pair out of the plurality of transistor pairs and applying the selection signal to the selected transistor pair to render the transistor pair conductive, as well as selecting at least another transistor pair out of the plurality of transistor pairs in response to the test enable signal and applying the selection signal to the selected transistor pair to render the transistor pair conductive. Thus, the total parasitic capacitance of the main and the sub-bit lines increases, so that an accelerated test of a read operation margin can be carried out.

REFERENCES:
patent: 5359566 (1994-10-01), Furuyama
patent: 5500821 (1996-03-01), Tanaka
"A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme" IEEE International Solid-State Circuits Conference, 1994, pp. 140-141.
"A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme" ISSCC Slide Supplemental, 1994, pp. 106-107.
"Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" IEEE, 1994, pp. 454-458.

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