Semiconductor memory device including improved redundancy circui

Details Semiconductor memory device including improved redundancy circui Semiconductor memory device including improved redundancy circui

1995-04-05

1997-03-18

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523003, G11C 700, G11C 2900

Patent

active

056129173

ABSTRACT:
A dynamic random access memory includes memory cell array blocks, row decoders, redundant word lines, redundant memory cells, replacement circuits, and a normal memory cell de-select circuit. Each memory cell array block includes normal word lines and normal memory cells. Each row decoder is provided corresponding to one memory cell array block. Any of the redundant word line is provided corresponding to one memory cell array block. Each replacement circuit includes a redundancy select circuit, a replacement address program circuit, and a redundant word line select circuit. The redundancy select circuit has set in advance whether a corresponding redundant word line is to be used or not. The program circuit has an address programmed of a normal word line to be replaced with a corresponding redundant word line. The normal memory cell de-select circuit inactivates a row decoder in response to an output of the replacement circuit when any replacement circuit selects a corresponding redundant word line. When a corresponding redundant word line is not used, a predecode signal is distributed to a program circuit so that the loads of a predecode signal are equal to each other.

REFERENCES:
patent: 5357470 (1994-10-01), Namekawa et al.
patent: 5392247 (1995-02-01), Fukita
patent: 5475648 (1995-12-01), Fujiwara
patent: 5487039 (1996-01-01), Sukegawa

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