Multi-block erase and verification circuit in a nonvolatile semi

Details Multi-block erase and verification circuit in a nonvolatile semi Multi-block erase and verification circuit in a nonvolatile semi

1997-11-21

1998-11-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

36418533, G11C 1300

Patent

active

058417214

ABSTRACT:
A multi-block erase circuit in nonvolatile semiconductor memory device comprises a plurality of memory blocks composed of a plurality of memory cells formed on a semiconductor substrate, each memory cell composed of at least one memory transistor with a floating gate and a control gate, and a plurality of block selectors connected to the memory blocks to select the control gates of the memory transistors within a selected memory block and to erase the memory transistors during an erase operation, wherein each block selector has storing means for storing block selection flags to select the control gates of the memory transistors within at least one selected memory block during the erase operation and for storing reset flags to float the control gates of the memory transistors within the remaining unselected memory blocks, thereby erasing simultaneously only the memory transistors within the selected memory blocks during the erase operation.

REFERENCES:
patent: 5065364 (1991-11-01), Atwood

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