Memory having and method for testing redundant memory cells

Details Memory having and method for testing redundant memory cells Memory having and method for testing redundant memory cells

1996-11-27

1998-11-24

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, 36523006, G11C 2900

Patent

active

058417095

ABSTRACT:
A memory device includes an array of matrix memory cells that each correspond to a matrix location within the matrix array, an array of redundant memory cells that each correspond to a redundant location within the redundant array, and address and test circuitry. During a first test mode that is performed before any redundant cells have been mapped to the addresses of matrix locations, the address and test circuitry simultaneously addresses all of the matrix locations and selects all of the redundant memory cells. During a second test mode that is performed after the first test mode, the address and test circuitry simultaneously addresses all of the matrix locations and selects only those redundant memory cells that are mapped to the addresses of matrix locations. Typically, the redundant memory cells are so mapped to replace defective matrix memory cells.

REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4573146 (1986-02-01), Graham et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4689494 (1987-08-01), Chen et al.
patent: 4714839 (1987-12-01), Chung
patent: 4734889 (1988-03-01), Mashiko et al.
patent: 4791615 (1988-12-01), Pelley, III et al.
patent: 4829480 (1989-05-01), Seo
patent: 4833652 (1989-05-01), Isobe et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 4860260 (1989-08-01), Saito et al.
patent: 4985866 (1991-01-01), Nakaizuri
patent: 5034925 (1991-07-01), Kato
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5091884 (1992-02-01), Kagami
patent: 5107464 (1992-04-01), Sahara et al.
patent: 5113371 (1992-05-01), Hamada
patent: 5124948 (1992-06-01), Takazawa et al.
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5177743 (1993-01-01), Shinoda et al.
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5262994 (1993-11-01), McClure
patent: 5281868 (1994-01-01), Morgan
patent: 5295102 (1994-03-01), McClure
patent: 5299161 (1994-03-01), Choi et al.
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5307316 (1994-04-01), Takemae
patent: 5311472 (1994-05-01), Ota
patent: 5327382 (1994-07-01), Seno et al.
patent: 5337278 (1994-08-01), Cho
patent: 5355340 (1994-10-01), Coker et al.
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5404331 (1995-04-01), McClure
patent: 5455798 (1995-10-01), McClure
patent: 5471426 (1995-11-01), McClure
patent: 5530674 (1996-06-01), McClure et al.
patent: 5544106 (1996-08-01), Koike
patent: 5572470 (1996-11-01), McClure et al.
patent: 5574688 (1996-11-01), McClure et al.
patent: 5608678 (1997-03-01), Lysinger
patent: 5631868 (1997-05-01), Termullo, Jr. et al.
Nishimura et al., "A Redundancy Test-Time Reduction Technique in 1-Mbit DRAM with a Multibit Test Mode," IEEE Journal of Solid-State Circuits 24(1):43-49, 1989.
Kayano et al., "25-ns 256K .times.1/64K .times.4 CMOS SRAM's," IEEE Journal of Solid-State Circuits SC-21(5):686-690, 1986.
Childs et al., "An 18 ns 4K .times.4 CMOS SRAM," IEEE J. Solid State Circuits SC-19(5):545-51, 1984.
Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line," IEEE J. Solid-State Circuits SC-19(5):578-585, 1984.
Hardee et al., "A Fault-tolerant 20 ns/375 mW 16K .times.1 NMOS Static Ram," IEEE J. Solid-State Circuits Sc-16(5):435-443, 1981.

Affiliated with

Also associated with

Rating

Memory having and method for testing redundant memory cells does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory having and method for testing redundant memory cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory having and method for testing redundant memory cells will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1710684