Multilayer module with thinfilm redistribution area

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

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257723, 257758, H01L 2334

Patent

active

059145331

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to an improved multilayer module for packaging of at least one electronic component and to a method for fabricating such a multilayer module.
As VLSI circuits become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed of state of the art VLSI devices. Present day modules made of ceramic, typically multilayered ceramic modules are normally mounted onto cards or boards, with cards or boards combined together to form the central processing unit (CPU) of a computer. The multilayered ceramic (MLC) modules typically have VLSI chips mounted on the topsurface and typically have pins on the bottomsurface thereof even though there are multilayer ceramic modules which have alternative mounting means such as solderbumps.
As integrated circuit speeds and packaging densities-increase the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects and the like in the packaging become significant. Such inductance effects may arise from, for example, switching and the like, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk, and the like.
The multilayer ceramic (MLC) multichip module (MCM) technology introduced by IBM represents a revolutionary advance in packaging state of the art and provides the high-performance wiring needed to exploit the gains achieved with todays integrated circuits logic devices. This technology is described for example in A. J. Blodgett, "A Multilayer Ceramic Multi-Chip Module," Proceedings of the Electronic Components Conference, IEEE, New York, 1988, pp. 283-285 and B. T. Clark and Y. M. Hill, "IBM Multichip Multilayer Ceramic Modules for LSI Chips--Designs For Performance and Density," IEEE Transactions Components, Hybrids. Manuf. Technology, CHMT-3, 89-93 (1980). Furthermore, the articles by A. J. Blodgett, D. R. Barbour, "Thermal Conduction Module: A High-Performance Multilayer Ceramic Package", IBM J. Res. Develop., vol. 26, no. 1, January 1982, and by A. J. Blodgett, "Microelectronic Packaging", Scientific American, July 1983, vol. 249, no. 1 describe this technology.
Even though the above referenced IBM technology mainly relies on thickfilm technology for the production of multilayer modules, proposals have been made in the prior art to combine thickfilm and thinfilm technology for the packaging of integrated circuits chips. U.S. Pat. No. 4 958 258 describes a modular hybrid microelectronic structure with a high density of integration. The structure comprises, on one face, an encapsulated hybrid circuit that groups together circuits with a high density of integration, formed by one or more semiconductor chips, said circuits being mounted on a thin-layer substrate. The thin-layer substrate is grown on a face of supporting, thick-layer substrate, preferably made of co-baked ceramic. Encapsulate, microelectronic components such as monolithic, integrated circuits are borne on the other face of the substrate. The interconnections among various components and with the exterior are made within and through the layers of the supporting substrate so that no wire or connection appears on the uncovered parts of the substrate.
Furthermore U.S. Pat. No. 4 549 200 and U.S. Pat. No. 4 916 259 propose the combination of thickfilm and thinfilm technologies for the production of packaging modules.
The fast development of the VLSI/ULSI CMOS chip technology aims to further increase the circuit density. This goes hand in hand with a corresponding increase in the number of I/O counts of a chip which is made possible by the FLIP CHIP technology, especially by the C4-technology. Todays multilayer module technologies are mainly based on either multilayer ceramic or multilayer glass-ceramic thickfilm technology. In both cases the line width, line spacing and insulator thickness are limited by the accompanying thickfilm technologies. The sa

REFERENCES:
patent: 5475264 (1995-12-01), Sudo et al.

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