Semiconductor device having cladding layer and process for produ

Details Semiconductor device having cladding layer and process for produ Semiconductor device having cladding layer and process for produ

1993-01-13

1995-05-09

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257311, 257350, 257401, 257618, H01L 2968, H01L 2348

Patent

active

054142857

ABSTRACT:
An SOI semiconductor device, for example, a DRAM device, wherein a dummy pattern layer of substantially the same thickness as a charge storage layer constituting part of a capacitor is formed by the same material as the layer in a cell nonformation region wherein memory cells are not formed around a cell formation region where memory cells are formed in an array. As a result, the large step-difference between the cell formation region and the cell nonformation region disappears, the surface of the smoothing layer formed under the charge storage layer and dummy pattern layer become smooth, air bubbles do not become entrained between the smoothing layer and supporting substrate, and the bonding of the smoothing layer and the supporting substrate becomes better. The dummy pattern layer preferably is fixed to a predetermined potential in a range from the ground level to the power source voltage. Further, the dummy pattern layer preferably is electrically connected to a cell plate layer stacked on the charge storage layer through a capacitor insulating film layer.

REFERENCES:
patent: 4969022 (1990-11-01), Nishimoto et al.
patent: 4990463 (1991-02-01), Mori
patent: 5028558 (1991-07-01), Haisma et al.
patent: 5096854 (1992-03-01), Saito et al.
patent: 5162881 (1992-11-01), Ohya

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