Vertically stacked vertical transistors used to form vertical lo

Details Vertically stacked vertical transistors used to form vertical lo Vertically stacked vertical transistors used to form vertical lo

1994-01-25

1997-03-18

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, H01L 2976, H01L 2994

Patent

active

056125631

ABSTRACT:
A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

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"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's", by Hiroshi Takato et al., was published in IEEE Trans. on Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 573-577.

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