Programmable delay element

Details Programmable delay element Programmable delay element

1997-01-21

1998-11-24

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Field-effect transistor

326 44, 326 93, 326 95, H03K 19094

Patent

active

058412964

ABSTRACT:
The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and refabrication of the circuit. The invention provides programmable memory cells coupled to a capacitive load via a plurality of switches. The capacitive load is coupled to a signal path and comprises a plurality of capacitors. The programmable memory cells selectively turn on the switches coupled to the capacitive load. In one FPGA implementation, the programmable memory cells are implemented in IOBs and are loaded with appropriate data during a device configuration stage. Delay equalization can be achieved by programming the memory cells such that the delays seen by device I/O pins are equal between IOBs and pads. The invention also provides a slew rate control circuit for an inverter or a buffer to provide an optimal slew rate. The slew rate control circuit comprises a plurality of memory cells coupled to a current mirror via a plurality of switches. Appropriate data are programmed or loaded into the memory cells to selectively turn the switches coupled to a current source on or off. The current mirror is also coupled to the inverter or buffer to control its supply current. The slew rate of the inverter or buffer is controlled via the memory cell programming.

REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4959564 (1990-09-01), Steele
patent: 5012143 (1991-04-01), Boudewijns
patent: 5160863 (1992-11-01), Hui
patent: 5287025 (1994-02-01), Nishimichi
patent: 5384497 (1995-01-01), Britton et al.
patent: 5459422 (1995-10-01), Behrin
patent: 5644496 (1997-07-01), Agrawal et al.
patent: 5650739 (1997-07-01), Hui et al.
patent: 5705942 (1998-01-01), Ashuri
H.B. Bakoglu, "Circuits, Interconne tions, and Packaging for VLSI," Chapter 8, Section 6, pp. 358-360, Addison-Wesley, 1990 (ISBN 0-201-06008-6).
T. Gabara et al., "Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers," IEEE Custom Integrated Circuits Conference, pp. 277-280, May, 1996.

Affiliated with

Also associated with

Rating

Programmable delay element does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable delay element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable delay element will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1707197