Hybrid programmable logic device

Details Hybrid programmable logic device Hybrid programmable logic device

1996-02-09

1998-11-24

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K 19177

Patent

active

058412956

ABSTRACT:
A programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The integrated circuit can include a first number of the look up tables and a second number of the programmable logic array-like circuits and where the first and second numbers are related by a ratio of between 0.25:1 and 6:1, between 1:1 and 5:1, or about 4:1. The programmable logic array-like circuits can each include at least 10,000 or 50,000 equivalent two-input NAND gates, and the look up tables and the programmable logic array-like circuits can each comprise static random access cells. A method of implementing a logic circuit includes reading a netlist that includes a plurality of subnets. The method also includes determining the suitability of ones the subnets to being implemented with look up tables and with programmable logic array-like circuits, and determining whether to implement each subnet with a lookup table or a programmable logic array-like circuit based on results of the step of determining. Based on the steps of determining, the method implements a first subset of the plurality of subnets with look up table circuits and a second subset of the plurality of subnets with programmable logic array-like circuits.

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Wilson, Ron "System-level programs debut", Special Issue (Dec. 15, 1995) Electrical Engineering Times pp. 20, 80 and 81.
Stansfield, Anthony and Page, Ian "The Design of a New FPGA Architecture*" A paper published in Field Programmable Logic 95, a workshop held in England in August of 1995 (14 pages).

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