Reduction of via over etching for borderless contacts

Details Reduction of via over etching for borderless contacts Reduction of via over etching for borderless contacts

1996-03-15

1998-11-24

Trinh, Michael

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438653, 438761, 438791, H01L 214763, H01L 2144

Patent

active

058406247

ABSTRACT:
A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

REFERENCES:
patent: 4732801 (1988-03-01), Joshi
patent: 4966870 (1990-10-01), Barber et al.
patent: 5164334 (1992-11-01), Mizushima
patent: 5350712 (1994-09-01), Shibata
patent: 5393703 (1995-02-01), Olowolafe et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 5561084 (1996-10-01), Takata
patent: 5571751 (1996-11-01), Chung
patent: 5587338 (1996-12-01), Tseng
patent: 5599740 (1997-02-01), Jang et al.
patent: 5612254 (1997-03-01), Mu et al.

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