Highly stable semiconductor memory with a small memory cell area

Details Highly stable semiconductor memory with a small memory cell area Highly stable semiconductor memory with a small memory cell area

1990-10-29

1992-07-28

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 365156, 36518905, G11C 1140, G11C 800

Patent

active

051345811

ABSTRACT:
In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

REFERENCES:
patent: 4623989 (1986-11-01), Blake
patent: 4760561 (1988-07-01), Yamamoto et al.
S. Yamamoto et al., "A 256K CMOS RAM with Variable-Impedance Loads" ISSCC Feb. 13, 1985, pp. 58-59.
T. Toyabe et al., "A Soft Error Rate Model for MOS Dynamic RAM'S", IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1, 1982, pp. 732-737.
K. Yuzuriha et al., "A New Process Technology for a 4Mbit SRAM with Polysilicon Load Resistor Cell" 1989 Syposium A VLSI Technology, Digest of Technical Papers pp. 61-62.
K. Ishibashi, "An .alpha.-immune 2V Suply Voltage SRAM Using Polysilicon PMOS Load Cell" 1989 Symposium on VLSI Circuit, Digest of Technical Papers, pp. 29-30.
"A New Isolation Technology for VLSI", Extended Abstracts of the 17th Conf. on Solid State Devices and Materials, 1985 pp. 337-340 (Nojiri et al).
T. Kaga et al, "Advanced OSELO Isolation with Shallow Grooves for Three-quarter Micron ULSIs", Extended Abstracts of 18th (1986 Int'l) Conference on Solid State Devices and Materials, pp. 61-64.

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