Clock redundancy system

Details Clock redundancy system Clock redundancy system

1998-07-10

2000-02-08

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

713502, G06F 106

Patent

active

060237716

ABSTRACT:
An information processing apparatus of the present invention is, in order to prevent a malfunction by an increase or a decrease of an oscillation frequency of a clock oscillator, provided with redundancy with 2n+1 (n is a positive integer) clock oscillators and includes a counter for counting a clock of each of the clock oscillators. Values of the counters are compared with each other at every certain timing to select a normal clock oscillator, and the clock of the oscillator is used by modules of the information processing apparatus. Accordingly, even if a little disorder in oscillation frequency occurs with any of the clock oscillators, the information processing apparatus continues to operate without stopping and without malfunctioning. Further, a difference between each two values is calculated, and an error is discriminated when the difference is higher than a certain value. By making it possible to freely set the value to be used for the discrimination of an error, it is possible to set a displacement in oscillation frequency of a clock oscillator which is to be discriminated as an error.

REFERENCES:
patent: 4672639 (1987-06-01), Tanabe et al.
patent: 5479644 (1995-12-01), Hongo
patent: 5574757 (1996-11-01), Ogawa

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