Method of fabricating integrated circuit wiring with low RC time

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438622, 438671, 438672, 438687, H01L 214763

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active

060372486

ABSTRACT:
The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is in electrical contact with the substrate assembly through the portion of the metal layer that fills the openings. The portion of the metal layer that fills the openings supports the elevated portion of the metal layer. A method of fabricating a semiconductor interconnect structure is also provided. A resist layer is patterned on a substrate assembly to define openings. A metal layer is deposited on the resist layer and into the openings, and the resist layer is removed to form a gap between the metal layer and the underlying substrate assembly.

REFERENCES:
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5071518 (1991-12-01), Pan
patent: 5272111 (1993-12-01), Kosaki
patent: 5354712 (1994-10-01), Ho et al.
patent: 5391921 (1995-02-01), Kudoh et al.
patent: 5556812 (1996-09-01), Leuschner et al.
patent: 5639686 (1997-06-01), Hirano et al.
Togo, M. et al., "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs," 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
Anand, M. et al., "NURA: A Feasible, Gas-Dielectric Interconnect Process," 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 82-83.
Parameswaran, M. et al., "A New Approach for the Fabrication of Micromechanical Structures," Sensors and Activators, vol. 19, pp. 289-307 (1989).
Carley, L., et al., "Fabrication and Performance of Mesa Interconnect," Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Aug. 1996, pp. 133-37.

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