Multi bank test mode for memory devices

Details Multi bank test mode for memory devices Multi bank test mode for memory devices

1997-02-04

1999-11-30

Grant, William

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714710, 714718, 714765, 714720, 370352, 370355, 370376, 370438, 370463, 36518905, 36523003, 365200, 365201, 379191, 379193, 379253, 379255, G11C 2900

Patent

active

059961066

ABSTRACT:
A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

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