Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-05-28
1999-11-30
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
711100, G01R 3128
Patent
active
059960981
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a memory testing apparatus for testing a memory, for example, a memory called random access memory (hereinafter referred to as RAM) which is readable and writable, and more particularly, to an improvement in a memory testing apparatus provided with a mask pattern memory.
BACKGROUND ART
A memory testing apparatus for testing a memory such as RAM generally comprises a timing generator, a pattern generator, a waveform generator, a logical comparator and a failure analysis memory. As is well known, a memory of this kind is often constructed in the form of a semiconductor integrated circuit element. In the following discussion, a case will be described in which the memory testing apparatus tests a memory formed as a semiconductor integrated circuit element (hereinafter referred to as IC memory), by way of example, in order to facilitate understanding of the invention. However, it should be understood that the apparatus can also test memories other than IC memories.
A pattern generator generates, in response to a reference clock (operating clock) supplied from a timing generator, address pattern data, test pattern data, control signals and the like which are to be applied to an IC memory to be tested (IC memory under test), and in addition thereto, generates expected value pattern data and the like which are to be fed to a logical comparator.
An IC memory to be tested which is commonly called MUT (memory under test) is controlled in writing of a test pattern signal therein or reading of a test pattern signal therefrom by application of a control signal thereto. Specifically, when a writing control signal is applied to the IC memory under test, a test pattern signal is successively written in the IC memory under test at an address thereof specified by an address pattern signal, and when a reading control signal is applied to the IC memory under test, the test pattern signal previously written in the IC memory under test is successively read out thereof at an address specified by an address pattern signal.
A response output signal read out of the IC memory under test (hereinafter also referred to simply as memory under test) is supplied to the logical comparator where it is logically compared with an expected value pattern data outputted from the pattern generator. If a result of comparison in the logical comparator indicates an anti-coincidence or a mismatch, the logical comparator outputs a defective signal representing the anti-coincidence, namely, so-called failure data. The logical comparator usually outputs logical "1" having a high logical level (logic H) as a failure data. By contrast, if a result of comparison indicates a coincidence, the logical comparator outputs a defectless signal representing the coincidence, namely, so-called pass data. Since failure data is represented by logical "1", pass data is outputted as logical "0" having a low logical level (logic L). The failure data is fed to and stored in the failure analysis memory.
The failure analysis memory has the same operating rate or speed and storage capacity as those of the memory under test, and the same address pattern signal as that applied to the memory under test is applied to the failure analyses memory. In addition, the failure analysis memory is initialized prior to the start of a test. For example, when initialized, the failure analysis memory has data of logical "0s" written in all of the addresses thereof. Every time a failure data is generated from the logical comparator during a test of a memory under test, a failure data of logical "1" is written in the address of the failure analysis memory specified by the address pattern signal. That is, in a memory cell of the failure analysis memory having the same address as that of the failure memory cell of the memory under test is written the failure data (logical "1") indicating that failure memory cell of the memory under test.
Upon completion of one test cycle, a decision is rendered as to whether the memory under test is pass or fai
REFERENCES:
patent: 4369511 (1983-01-01), Kimura et al.
patent: 5357473 (1994-10-01), Mizuno et al.
patent: 5909448 (1999-06-01), Takahashi
Advantest Corporation
Lathrop David N.
Tu Trinh L.
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