Semiconductor memory device with a redundant decoder having a sm

Details Semiconductor memory device with a redundant decoder having a sm Semiconductor memory device with a redundant decoder having a sm

1998-10-30

2000-02-08

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, 36523003, 36518509, G11C 2900

Patent

active

060234334

ABSTRACT:
In a semiconductor memory device comprising a regular memory cell array, a regular decoder, a redundant memory cell array, and a redundant decoder, the redundant decoder comprises a plurality of redundant decoding circuits each of which is supplied with a test mode signal. The redundant decoding circuits are supplied with an address signal and a complementary address signal in different order so that at least one pair of a bit in the address signal and a corresponding bit in the complementary address signal is supplied in the reverse sequence. The redundant decoder further comprises a decode inhibit signal producing arrangement for producing a decode inhibit signal indicative of active when any one of the redundant decoding circuits produces a redundant decoded signal indicative of active. Responsive to the decode inhibit signal indicative of inactive, the regular decoder decodes the address signal and the complementary address signal into a regular decoded signal for activating one of regular memory cells in the regular memory cell array. Each redundant decoding circuit comprises a test fuse circuit including a test fuse-element. The test fuse circuit produces a test fuse output signal indicative of active when the test fuse-element is not fused.

REFERENCES:
patent: 5519657 (1996-05-01), Arimoto
patent: 5544106 (1996-08-01), Koike
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patent: 5612917 (1997-03-01), Kozawa et al.
patent: 5612918 (1997-03-01), McClure
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patent: 5771195 (1998-06-01), McCLure
patent: 5781486 (1998-07-01), Merritt
patent: 5790462 (1998-08-01), McClure

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