Stacked ferroelectric memory cell

Details Stacked ferroelectric memory cell Stacked ferroelectric memory cell

1994-06-10

1996-02-27

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257298, 257300, 257306, 365 65, 365145, 365149, H01L 2978, H01L 2992, H01L 5100, H01G 706

Patent

active

054951178

ABSTRACT:
A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

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patent: 5024964 (1991-06-01), Rohrer et al.
patent: 5046043 (1991-09-01), Miller et al.
Kinney et al., "A Non-Volatile Memory Cell Based on Ferroelectric Storage Capacitors", IEEE IEDM, 1987, pp. 850-851.
Womach et al., "A 16kb Ferroelectric Nonvolatile Memory With A Bit Parallel Architecture", IEEE International Solid-State Circuits Conference (Feb., 1989).

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