Semiconductor chip package with dual layer terminal and lead str

Details Semiconductor chip package with dual layer terminal and lead str Semiconductor chip package with dual layer terminal and lead str

1998-05-29

1999-11-30

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257776, 257780, 257692, H01L 2348, H01L 2352, H01L 2940

Patent

active

059947810

ABSTRACT:
An assembly for packaging a microchip has a dielectric element including a top dielectric layer having a bottom surface. Traces extend at the bottom surface to connect terminals of the dielectric layer to conductive elements, the conductive elements being connected to contacts on a chip. Each trace has a terminal to which it is electrically connected. Traces extend beneath terminals to which they are not electrically connected.

REFERENCES:
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.

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