Semiconductor package with multilayer circuit, and semiconductor

Details Semiconductor package with multilayer circuit, and semiconductor Semiconductor package with multilayer circuit, and semiconductor

1997-07-29

1999-11-30

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257701, 257773, H01L 23053

Patent

active

059947713

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor package with a multilayer circuit, and a semiconductor device.


BACKGROUND ART

A semiconductor package (produced by a so-called build-up system) has been known in the prior art and is shown in FIG. 3. In the built-up system a film-like circuit pattern 22 is overlaid via a film-like insulation layer (resist) 18 on a core member 10 carrying a circuit pattern 12 made of metallic foil on the surface thereof, and electrically connected to the circuit pattern 12 on the core member 10 to form a multilayer circuit. The circuit pattern 12 provided on the surface of the core member 10 is made, for example, of copper foil. A solder resist 26 is coated on the upper surface of the uppermost film-like circuit pattern 22. A ball bump 30 is fixed to the circuit pattern 22 at a position where the solder resist 26 is partially removed. Thus, the semiconductor package is formed. A semiconductor chip 14 is fixed to the film-like circuit pattern 22 in the uppermost layer and connected to the multilayer circuit. Further, the semiconductor chip 14 or others are sealed by a potting substance (not shown) to form a semiconductor device.
According to the above semiconductor package, since the multilayer circuit is formed by using the film-like resist 18 and the film-like circuit pattern 22, it is possible to make the package very dense and miniaturize the circuits in response to the dense integration of the semiconductor chip 14.
However, when the semiconductor package is produced by the build-up system as described above, the bonding force between the coated resist 18 and the copper-plated film-like circuit pattern 22 is weak. That is, since the film-like circuit pattern 22 is merely overlaid with the resist 18, the bonding force is very weak and is, for example, in a range from 0.2 kg/cm to 0.3 kg/cm.
Accordingly, a bonding force is also weak between the ball bump 30 fixed on the surface of the film-like circuit pattern 22 and the resist 18. Since the semiconductor chip 14 is fixed to the uppermost film-like circuit pattern 22 via the ball bump 30, the semiconductor chip 14 cannot be assuredly fixed, with a high yield, to the semiconductor package and this results in a problem of lack of reliability and durability. For example, when the ball bump 30 is fixed, the film-like circuit pattern 22 may be peeled off or the semiconductor chip 14 may be released from the semiconductor package to disconnect the electric connection between the semiconductor chip 14 and the multilayer circuit.
Also, when the semiconductor chip is connected to the multilayer circuit of the semiconductor package by a wire bonding system, there is problem in that, if the bonding ability of the film-like circuit pattern 22 with the resist 18 is inferior, it is impossible to bond wires to the film-like circuit pattern 22 with a high yield to result in the deterioration of reliability and durability.


DISCLOSURE OF INVENTION

An object of the present invention is to assuredly fix a semiconductor chip to a semiconductor package formed by a so-called build-up system so that the yield and the durability of a semiconductor device thus obtained is improved.
To achieve this object, according to the present invention, a semiconductor package is provided which comprises an insulating core substrate defining a semiconductor chip mounting area on part of a first surface thereof, a circuit pattern formed on the first surface of the core substrate with a metallic foil so that one end of the circuit pattern extends into the semiconductor chip mounting area, and at least one film-like circuit pattern connected to the former circuit pattern and formed in an area around the semiconductor chip mounting area on the first surface of the core substrate via a film-like insulating layer, wherein the semiconductor chip mounting area is formed as a recess on the first surface of the core substrate with the film-like circuit pattern and the film-like insulating layer, and the interlayer electric connection is provided bet

REFERENCES:
patent: 4640010 (1987-02-01), Brown
patent: 5041943 (1991-08-01), Ilardi et al.
patent: 5306670 (1994-04-01), Mowatt et al.
patent: 5521332 (1996-05-01), Shikata et al.
patent: 5828126 (1998-10-01), Thomas

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