Method of fabricating aluminum-indium (or thallium) vias for ULS

Details Method of fabricating aluminum-indium (or thallium) vias for ULS Method of fabricating aluminum-indium (or thallium) vias for ULS

1998-01-30

1999-11-30

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438678, 257750, 257752, H01L 2348, H01L 2354

Patent

active

059942215

ABSTRACT:
The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method comprises the steps of forming a metal alloy within the opening. The metal alloy comprises at least a first and a second metal with the first metal selected from a Group 13 metal and having a melting point substantially lower than a melting point of the second metal and the dielectric. This particular method further comprises the steps of subjecting the first and second metals to a temperature sufficient to melt the first metal and reflow the metal alloy.

REFERENCES:
patent: 3281239 (1966-10-01), Reding et al.
patent: 3413157 (1968-11-01), Kuiper
patent: 4098606 (1978-07-01), Despic et al.
patent: 4970176 (1990-11-01), Tracy et al.
patent: 5518674 (1996-05-01), Powell et al.
patent: 5534463 (1996-07-01), Lee et al.
patent: 5633199 (1997-05-01), Fiordalice et al.
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5789818 (1998-08-01), Havemann
patent: 5879808 (1999-03-01), Wary et al.
patent: 5888899 (1999-03-01), Paranjpe
patent: 5904499 (1999-05-01), Pace
patent: 5917707 (1999-06-01), Khandros et al.
K. Kikuta and T. Kikkawa; A1-Ge Reflow Sputtering for Submicron Contact Hole Filling; J. Electrochem. Soc., vol. 143, No.1, Jan. 1996; pp. 228-232.
G.A. Dixit, M.F. Chisholm, M.K. Jain, T. Weaver, L.M. Ting, S. Poarch, K. Mizobuchi and R. H. Havemann; A Novel High Pressure Low Temperature Aluminum Plug Technology for Sub-0.5.mu.m Contact/Via Geometries; 1994 IEDM; pp. 105-108.
B. Zhao, M.A. Biberger, V. Hoffman, S.-Q. Wang, P.K. Vasudev and T.E. Seidel; A Novel Low Temperature PVD Planarized A1-Cu Process for High Aspect Ratio Sub-Half Micron Interconnect; IEDM 1996; pp. 353-356.

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