Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1996-03-28
1999-11-30
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438692, H01L 21762
Patent
active
059941995
ABSTRACT:
A semiconductor device includes a plurality of single crystal semiconductor island layers formed on a semiconductor substrate with a first insulating layer intervened therebetween, the single crystal semiconductor island layers being isolated from one another by a second insulating layer. In forming the single crystal semiconductor island layers, a single crystal semiconductor layer is formed and is selectively removed on the first insulating layer. The second insulating layer is buried between adjacent ones of the single crystal semiconductor island layers. The second insulating layer is formed over the entire surface inclusive of the single crystal semiconductor island layers and a surface portion of the second insulating layer is removed by an etching process or a polishing process. Since the non-element regions are buried by the second insulating layer and the single crystal semiconductor island layers are completely isolated from one another, the substrate-related capacitances such as those at wiring regions and resistive parts are reduced.
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Fully SIO Isolated High Speed Self-Aligned Bipolar Transistor on Thin SOI by: H. Nishizawa etal, 1991 VLSI Symposium Technical Digest.
High Performance Complementary Bipolar Technology, By: J. Warnock etal, 1993 VLSI Symposium Technical Digest.
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Fourson George
NEC Corporation
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