Semiconductor-integrated-circuit SRAM-cell array with single-end

Details Semiconductor-integrated-circuit SRAM-cell array with single-end Semiconductor-integrated-circuit SRAM-cell array with single-end

1995-09-01

1996-07-30

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Flip-flop

36518904, G11C 1140

Patent

active

055418740

ABSTRACT:
Each memory cell in an SRAM array contains an auxiliary reading transistor connected across one of the transistors in each cell. A row read line controls the ON-OFF condition of this auxiliary reading transistor. In addition, each cell has two access transistors for connecting the cell to complementary column bit lines The ON-OFF condition of both of these access transistors is controlled by a row write line. Each cell has two power nodes, one connected to a power source such as VDD and the other connected to a column detector line that terminates in a current sensor. The state of the memory cell is sensed by this current sensor. In one embodiment, the power line that brings the voltage VDD to the cells is a column line; in another embodiment, it is a row line. Thus there are a total of four column lines and two row lines in the one embodiment, and a total of three column lines and three row lines in the other embodiment.

REFERENCES:
patent: 5282174 (1994-01-01), Little
patent: 5321658 (1994-06-01), Ishimura et al.

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