Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1987-07-24

1989-03-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, G11C 700

Patent

active

048170569

ABSTRACT:
In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. The comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit or its inversion of the input address to be opened or closed depending on the value of the particular bit of the input address currently applied, and a PROM element in series with the gate element. The dynamic NOR gate has a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element is connected across the first and the second nodes. The potential on the second node is caused to be identical with the potential on the first node during the precharge period.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4392211 (1983-07-01), Nakano et al.
patent: 4428068 (1984-01-01), Baba
patent: 4656610 (1987-04-01), Yoshida et al.
"A Fault-Tolerant 64K Dynamic RAM", R. P. Cenker et al., ISSCC 79, Digest of Technical Papers, pp. 150-151, Feb. 1979.
"Equipping a Line of Memories with Spare Cells", Abbott et al., Electronics, Jul. 28, 1981, pp. 127-130.

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