Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1995-05-24
1996-07-30
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 97, H03K 19096
Patent
active
055415369
ABSTRACT:
A circuit for evaluating logic inputs responsive to a reference clock, which circuit includes a first clock terminal for coupling with a first clock, the first clock being delayed from the reference clock by a first frequency dependent delay period. The circuit includes a second clock terminal for coupling with a second clock, the second clock being delayed from the reference clock by a second frequency dependent delay period. The inventive circuit further includes a first circuit stage, which includes a pulse generation circuit coupled to both the first clock terminal and the second clock terminal. In one embodiment, the first circuit stage further includes an output terminal, an evaluation device coupled to the output terminal and the pulse generation circuit. The first circuit stage also includes a precharge device coupled to the output terminal, a third clock terminal, and a first logic level, the third clock being delayed from the reference clock by a third frequency dependent delay period.
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Hudspeth David R.
Sun Microsystems Inc.
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