Semiconductor memory device with logic level responsive testing

Details Semiconductor memory device with logic level responsive testing Semiconductor memory device with logic level responsive testing

1989-11-27

1991-05-14

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 36523003, 371 211, G11C 700, G11C 2900

Patent

active

050162209

ABSTRACT:
A testing circuit for a semiconductor memory device is provided. An AND operation is performed on the data read out from each block of a memory cell array when the bit data written into each block of the memory cell array for testing is "1", and a NOR operation is performed on the data read out from each block of the memory cell array when the bit data written into each block of the memory cell array is "0". In this manner, even when the data read out from the blocks are all inverted in their logical states through error, such error can be detected.

REFERENCES:
patent: 4661930 (1987-04-01), Tran
patent: 4672582 (1987-06-01), Nishimura et al.
patent: 4692901 (1987-09-01), Kumanoya et al.
patent: 4860259 (1989-08-01), Tobita
patent: 4873669 (1989-10-01), Furutani et al.
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4916700 (1990-04-01), Ito et al.
"A 90 ns 4Mb DRAM in a 300 Mil Dip", by Mashiko et al., Intn'l Solid-State Circuits Conf. 1987, WAM 1.1, pp. 12, 13, 314, 315.
"A 90 ns 1Mb DRAM with Multi-Bit Test Mode" by Kumanoya et al., Intn'l. Solid-State Circuits Conf. 1985, FAM17.2, pp. 240, 241, 352.

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