Neural network implementation of a binary adder

Details Neural network implementation of a binary adder Neural network implementation of a binary adder

1990-02-01

1991-05-14

Shaw, Dale M.

Boots, shoes, and leggings

G06F 750

Patent

active

050162110

ABSTRACT:
A binary adder is provided for adding-processing in a high speed parallel manner two N bit binary digits. The binary adder is implemented using neural network techniques and includes a number of amplifiers corresponding to the N bit output sum and a carry generation from the result of the adding process; an augend input-synapse group, an addend input-synapse group, a carry input-synapse group, a first bias-synapse group a second bias-synapse group an output feedback-synapse group and inverters. The binary adder is efficient and fast compared to conventional techniques.

REFERENCES:
patent: 4651296 (1987-03-01), Koike
patent: 4660166 (1987-04-01), Hopfield
patent: 4904881 (1990-02-01), Castro
"A Reconfigurable CMOS Neural Network" by Hans Peter Graf et al., ISSCC 90/Feb. 15, 1990.
"A BiCMOS Analog Neural Network with Dynamically Updated Weights" by Takayuki Morishita et al., ISSCC 90/Feb. 15, 1990.

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