Cache coherency protocols with posted operations and tagged cohe

Details Cache coherency protocols with posted operations and tagged cohe Cache coherency protocols with posted operations and tagged cohe

1998-02-17

2000-11-07

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711122, 711141, G06F 1216

Patent

active

061450596

ABSTRACT:
A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

REFERENCES:
patent: 5671391 (1997-09-01), Knotts
patent: 5749095 (1998-05-01), Hagersten
patent: 5832276 (1998-11-01), Feiste et al.
patent: 5903908 (1999-05-01), Singh et al.
patent: 5946709 (1999-08-01), Arimilli et al.

Affiliated with

Also associated with

Rating

Cache coherency protocols with posted operations and tagged cohe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache coherency protocols with posted operations and tagged cohe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache coherency protocols with posted operations and tagged cohe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1652486