System for managing input/output address accesses at a bridge/me

Details System for managing input/output address accesses at a bridge/me System for managing input/output address accesses at a bridge/me

1998-03-27

2000-11-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

710 48, 710 15, 710 17, 710 18, 710260, 711202, G06F 1324, G06F 1312, G06F 1314, G06F 1210, G06F 1310

Patent

active

061450308

ABSTRACT:
An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

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