System for transferring frame data by transferring the descripto

Details System for transferring frame data by transferring the descripto System for transferring frame data by transferring the descripto

1998-09-03

2000-11-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

710 22, 710 35, 710 40, 710 55, 709208, 709212, 709217, 709222, 711 3, G06F 1314

Patent

active

061450162

ABSTRACT:
A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values. The memory management unit also includes a descriptor management unit for controlling DMA transfers between the transmit and receive buffers and the system memory. The descriptor management obtains descriptor lists from system memory based on descriptor index data supplied by the host CPU and verified as valid by the descriptor management, and releases control of the descriptor lists by writing to status locations in system memory.

REFERENCES:
patent: 5081547 (1992-01-01), Howell
patent: 5341476 (1994-08-01), Lowell
patent: 5490283 (1996-02-01), Chin
patent: 5828901 (1998-10-01), O'Toole et al.
patent: 5889778 (1999-03-01), Huscroft et al.
patent: 6041328 (2000-03-01), Yu

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