CMOS inverter using gate induced drain leakage current

Details CMOS inverter using gate induced drain leakage current CMOS inverter using gate induced drain leakage current

1998-10-22

2000-11-07

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, H01L 2976

Patent

active

061440752

ABSTRACT:
An inverter formed in a semiconductor substrate is disclosed. The inverter comprises: a p-well formed in the substrate, the p-well being the output of the inverter; a gate structure formed atop the p-well, the gate structure being the input of the inverter and being formed from a thin gate oxide layer underneath a conductive layer; an n- base formed adjacent to a first edge of the gate structure; a p+ structure formed within the n- base; and a n+ structure adjacent a second edge of the gate structure.

REFERENCES:
patent: 5172209 (1992-12-01), Chang
patent: 6025625 (2000-02-01), Chi
patent: 6088259 (2000-07-01), Chi
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 4, pp. 443-452 by Lin et al., Aug. 1976.

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