Semiconductor memory device with improved buffer for generating

Details Semiconductor memory device with improved buffer for generating Semiconductor memory device with improved buffer for generating

1991-12-06

1994-01-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

36518905, 365195, G11C 802

Patent

active

052787893

ABSTRACT:
A write enable buffer circuit for generating an internal write designating signal includes a gate circuit for inhibiting generation of the signal in response to an internal output designating signal which attains a settled state prior to a data outputting operation by a data outputting buffer. In data reading, the gate circuit forbids generation of an internal write designating signal to certainly hold the internal write designating signal in a disable state even if a noise is generated in data output. Thus, it is prevented that an internal write designating signal is erroneously generated due to noise in data output to bring data output buffer into an output high impedance state, and also the data input buffer is certainly maintained at an inactive state in data output.

REFERENCES:
patent: 4992983 (1991-02-01), Suzuki
patent: 5043944 (1991-08-01), Nakamura et al.
patent: 5155702 (1992-10-01), Mia
Osamu MINATO et al., "2K.times.8 Bit Hi-CMOS Static RAM's", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 656-600.

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