Method and apparatus for multiple latency synchronous dynamic ra

Details Method and apparatus for multiple latency synchronous dynamic ra Method and apparatus for multiple latency synchronous dynamic ra

1997-01-17

1998-09-22

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711167, 365194, 36518908, 365233, G06F 1200, G06F 1316

Patent

active

058130233

ABSTRACT:
A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.

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patent: 5511024 (1996-04-01), Atwood et al.
patent: 5526506 (1996-06-01), Hyatt
patent: 5544124 (1996-08-01), Zagar et al.

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