Single-side oxide sealed salicide for EPROMS

Details Single-side oxide sealed salicide for EPROMS Single-side oxide sealed salicide for EPROMS

1996-08-13

1998-09-22

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257320, 257384, 257385, 438264, 438267, H01L 29788, H01L 2976

Patent

active

058118535

ABSTRACT:
A method of forming a memory cell structure in a semiconductor substrate that does not have a shorting problem between a floating gate and a source/drain region of the substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided thereinbetween to prevent the occurrence of a short or the formation of a silicide bridge. The invention is also directed to a semiconductor device fabricated by the method.

REFERENCES:
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 4996572 (1991-02-01), Tanaka et al.
patent: 5036378 (1991-07-01), Lu et al.
patent: 5041886 (1991-08-01), Lee
patent: 5051796 (1991-09-01), Gill
patent: 5494838 (1996-02-01), Chang et al.
patent: 5576569 (1996-11-01), Yang et al.

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