Method and structure for implementing a cache memory using a DRA

Details Method and structure for implementing a cache memory using a DRA Method and structure for implementing a cache memory using a DRA

1997-03-05

1998-10-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711105, G06F 1208

Patent

active

058290265

ABSTRACT:
A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. The DRAM array is operated at a higher frequency than the frequency of the CPU bus clock signal, thereby reducing the access latency of the DRAM array. By operating the DRAM array at a higher frequency than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus.

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