Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-17
1998-10-27
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711133, 711137, 711139, 395383, G06F 1300, G06F 1212
Patent
active
058290257
ABSTRACT:
A computer system and method in which allocation of a cache memory is managed by utilizing a locality hint value included within an instruction. When a processor accesses a memory for transfer of data between the processor and the memory, that access can be allocated or not allocated in the cache memory. The locality hint included within the instruction controls if the cache allocation is to be made. When a plurality of cache memories are present, they are arranged into a cache hierarchy and a locality value is assigned to each level of the cache hierarchy where allocation control is desired. The locality hint may be used to identify a lowest level where management of cache avocation is desired and cache memory is allocated at that level and any higher level(s). The locality hint value is based on spatial and/or temporal locality for the data associated with the access. Data is recognized at each cache hierarchy level depending on the attributes associated with the data at a particular level. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.
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patent: 5652858 (1997-07-01), Okada et al.
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"Pentium Family User's Manual, Vol.2: 82496/82497 Cache Controller and 82491/82492 Cache SRAM Data Book;" Intel Corporation; 1994; pp. 2-1 to 2-10,3-1 to 3-23 & 4-1 to 4-13.
"i750, i860, i960 Processors and Related Products;" Intel Corporation; 1994; pp. 2-39 to 2-47.
Gossage Glenn
Intel Corporation
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