1996-12-13
1998-10-27
Sheikh, Ayaz R.
395739, G06F 946
Patent
active
058288910
ABSTRACT:
The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips. This device (10) is connected to a microprocessor (100) and N peripheral chips (200,210,230) through data/address busses (108,110) and it is also connected to a memory (150) by an additional bus (112). An interrupt operation starts when any one of the peripheral chips activates an interrupt signal through OR gate (220) detected by the microprocessor. The invention avoids to involve the microprocessor in the determination of the interrupt requester except for the generation of a common start.sub.-- address decoded by logic (180) for starting interrupt operations and a common end.sub.-- address decoded by logic (190) for ending it. Owing to the start.sub.-- address and the interrupt signals (173,174) received, latch (170) generates a translated address to memory (150) through a multiplexer (160) to start the corresponding interrupt routine stored at this translated address. The activation of any one of the peripheral chips leads to the reading of the corresponding interrupt routine stored in the memory without requiring any action of the microprocessor. The number of interrupt routines depends on the possible combinations of the N interrupt signals.
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IBM Technical Disclosure Bulletin, vol. 33, No. 9 Feb. 1991 "Single Line Interrupt to Microprocessor", pp. 179-181.
Benayoun Alain
Le Pennec Jean-Francois
Michel Patrick
Cockburn Joscelyn G.
International Business Machines - Corporation
Sheikh Ayaz R.
Wiley David A.
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