Semiconductor memory device with a stacked capacitance structure

Details Semiconductor memory device with a stacked capacitance structure Semiconductor memory device with a stacked capacitance structure

1997-01-22

1998-10-27

Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257303, 257381, 257385, 257756, 257774, H01L 27108

Patent

active

058280979

ABSTRACT:
A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers. The contact pad is electrically connected to the second element through the second penetrating hole. The lower electrode and the contact pad are made by using a same conductive layer. The dielectric and the pad insulating layer are made by using a same insulative layer. The upper electrode and the pad protection layer are made by using a same conductive layer.

REFERENCES:
patent: 5281837 (1994-01-01), Kohyama
patent: 5432732 (1995-07-01), Ohmi
patent: 5459688 (1995-10-01), Pfiester et al.
patent: 5563762 (1996-10-01), Leung et al.
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5652466 (1997-07-01), Sakao
patent: 5656853 (1997-08-01), Ooishi
T. Tokuyama et al., "MOS LSI Fabrication Technology", published by Nikkel McGraw-Hill Inc., 1885, pp. 177-178.
IEDM 94, Technical Digest, pp. 927-929, "A 0.29-.mu.m.sup.2 MIM-Crown Cell and Process Technologies for 1-Gigabit Drams", published 1994.

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