Simultaneous read-write IGFET memory cell

Details Simultaneous read-write IGFET memory cell Simultaneous read-write IGFET memory cell

1981-09-23

1984-05-08

Stellar, George G.

Static information storage and retrieval

Systems using particular element

Flip-flop

365189, 365190, G11C 700, G11C 1140

Patent

active

044478917

ABSTRACT:
In a random-access memory of the type comprising an array of memory cells each comprising two cross-coupled inverters, each memory cell is connected to a first address line in a column direction exclusively used for a write operation, a second address line in a column direction used exclusively for a read operation, two first complementary data lines in a row direction used exclusively for a write operation and a second data line in a row direction used exclusively for a read operation. The two complementary data lines are connected through gate elements to their corresponding complementary input-output nodes, respectively, in each cell and these gate elements are controlled by the first address line used exclusively for a write operation and the data line used exclusively for a read operation is connected to one of the complementary nodes through a gate element which in turn is controlled by the data line used exclusively for a read operation. The complementary data lines are connected to a drive circuit which delivers information to be stored while the data line used exclusively for a read operation is connected to a sense amplifier. Since the read and write operations can be carried out simultaneously but independently of each other, erratic operations can be avoided regardless of the timing relationships between the write and read operations.

REFERENCES:
IBM Technical Disclosure Bulletin vol. 23, No. 7A, Dec. 1980, p. 2822, Multi-Port Asymmetrical Memory Cell, Joy et al.
IBM Technical Disclosure Bulletin vol. 17, No. 11, Apr. 1975, p. 3337, IGFET Address Powered Schmidt Storage Cell, Sonoda.
IBM Technical Disclosure Bulletin vol. 17, No. 11, Apr. 1975, pp. 3338-3339, Low-Power FET Storage Cell, Linton et al.
IBM Technical Disclosure Bulletin vol. 22, No. 10, Mar. 1980, pp. 4555-4556 "Low Voltage Memory Cell" D. B. Fields.
IBM Technical Disclosure Bulletin vol. 22, No. 10, Mar. 1980, pp. 4553-4554 "Multi-Port Array Cell" R. T. Dennison et al.

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