Dynamic semiconductor memory cell with random access and method

Static information storage and retrieval – Systems using particular element – Semiconductive

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365174, G11C 1300, G11C 1140

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044765452

ABSTRACT:
A RAM memory cell in double polysilicon technology having improved packing density is attained by insulating neighboring active memory regions under a first polysilicon plane by ion implantation to increase the substrate doping of the surface of the semiconductor body whereby field shield insulation regions are generated by a transistor in the off-state and the memory regions are rendered self-conducting by the ion implantation so that with a voltage at the polysilicon-1-electrode of 0 volts, the full operating voltage can be written into the memory capacitor.

REFERENCES:
S. Matsue et al., "A. 256 K-Dynamic RAM"; ISSCC 80, Digest of Tech. Papers, (Feb. 1980), pp. 232-233.
J. A. Appels et al., "Local Oxidation of Silicon; New Technological Aspects", Philips Research Reports, vol. 26, No. 3, (Jun. 1971), pp. 157-156.
S. A. Abbas et al., "Low-Leakage, N-Channel Silicon Gate FET with a Self-Aligned Field Shield", IEEE Internat. Electron Devices Meeting, Tech. Digest, (Washington, D.C., Dec. 1, 1973), pp. 371-373.
C. N. Ahlquist et al., "A 16 384-Bit Dynamic RAM", IEEE J. of Solid-State Circuits, vol. SC-11, No. 5, (Oct. 1976), pp. 570-573.

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