Self-aligned double-gate MOSFET by selective lateral epitaxy

Details Self-aligned double-gate MOSFET by selective lateral epitaxy Self-aligned double-gate MOSFET by selective lateral epitaxy

1995-03-21

1997-02-18

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257350, 257412, H01L 2701, H01L 2712, H01L 2976

Patent

active

056043686

ABSTRACT:
A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

REFERENCES:
patent: 5315143 (1994-05-01), Tsuji
patent: 5461250 (1995-10-01), Burghartz et al.
"Ultrafast Low-Power Operation of p.sup.+ -n.sup.+ Double-Gate SOI MOSFETs" T. Tanaka et al 1994 Sym. on VLSI Techn.Dig.ofTech.Papers pp. 11-12 No Month.

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