Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-09-15
2000-05-02
Wright, Norman Michael
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 13, 714 11, G06F 1300
Patent
active
060584912
ABSTRACT:
A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.
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Bossen Douglas Craig
Chandra Arun
Dillon Andrew J.
Emile Volel
International Business Machines - Corporation
Ng Antony P.
Wright Norman Michael
LandOfFree
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