Enhanced register array accessible by both a system microprocess

Details Enhanced register array accessible by both a system microprocess Enhanced register array accessible by both a system microprocess

1998-09-25

2000-05-02

Nelms, David

Static information storage and retrieval

Addressing

Multiple port access

365200, G11C 800

Patent

active

060580666

ABSTRACT:
A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.

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