Semiconductor memory device capable of high speed operation and

Details Semiconductor memory device capable of high speed operation and Semiconductor memory device capable of high speed operation and

1998-11-18

2000-05-02

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 365196, G11C 700

Patent

active

060580534

ABSTRACT:
In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.

REFERENCES:
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 5379259 (1995-01-01), Fujita
patent: 5625596 (1997-04-01), Uchida
"A Flexible Redundancy Technique for High-Density DRAM's", M. Horiguchi, et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.

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