Method to form a ragged poly-Si structure for high density DRAM

Details Method to form a ragged poly-Si structure for high density DRAM Method to form a ragged poly-Si structure for high density DRAM

1998-01-28

2000-05-02

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, H01L 2120

Patent

active

060572051

ABSTRACT:
A method for fabricating a capacitor on a semiconductor device is disclosed herein. The method includes the following steps. A first dielectric layer is formed on the semiconductor device in which the semiconductor device has a substrate. Next, a second dielectric layer is formed on the first dielectric layer. Successively, the first dielectric layer, the second dielectric layer and the semiconductor device is etched to form a hole contacting the substrate. Subsequently, a first conductive layer is formed in the hole and on the second dielectric layer. The next step is to pattern the first conductive layer to form a bottom electric electrode of the capacitor. Next, a third dielectric layer is formed on the first conductive layer to make a portion of the first conductive layer that is not covered by the third dielectric layer. The next step is to oxidize the third dielectric layer and the first conductive layer. The silicon dioxide layer is thus formed. Subsequently, the silicon dioxide layer is removed, after which the third dielectric layer and the portion of the first conductive layer are etched untill the third dielectric layer on the top surface of the first conductive layer is removed. Next, a dielectric film is formed on the third dielectric layer. Finally, a second conductive layer is formed on the dielectric film to form a top electric electrode of the capacitor.

REFERENCES:
patent: 5670405 (1997-09-01), Tseng
patent: 5696014 (1997-12-01), Figura
patent: 5723373 (1998-03-01), Chang et al.
patent: 5817544 (1998-10-01), Tseng
patent: 5840606 (1998-11-01), Lee

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