Semiconductor memory with built-in defective bit relief circuit

Details Semiconductor memory with built-in defective bit relief circuit Semiconductor memory with built-in defective bit relief circuit

1988-01-12

1989-12-26

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365236, G11C 700, G11C 2900

Patent

active

048902624

ABSTRACT:
A semiconductor memory device which has a memory portion and a counter to count rows and/or columns of the memory portion, the counter being so constructed to return to a reset mode at the beginning of an address counting sequence when coming up to an arbitrary address such that an address or addresses corresponding to a region of the memory containing one or more defective memory cells and occurring after the arbitrary address are inaccessible. The counter thereby comprises a defective bit relief circuit built into the memory device.

REFERENCES:
patent: 3758761 (1973-09-01), Henrion
patent: 3993982 (1976-11-01), Tallent et al.
patent: 4458357 (1984-07-01), Weymouth et al.
patent: 4737935 (1988-04-01), Wawersig et al.
patent: 4748594 (1988-05-01), Iida

Affiliated with

Also associated with

Rating

Semiconductor memory with built-in defective bit relief circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory with built-in defective bit relief circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with built-in defective bit relief circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1580820