Nonvolatile JRAM cell using nonvolatile capacitance for informat

Details Nonvolatile JRAM cell using nonvolatile capacitance for informat Nonvolatile JRAM cell using nonvolatile capacitance for informat

1981-06-02

1984-07-10

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365184, 365149, G11C 1100

Patent

active

044596847

ABSTRACT:
Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.

REFERENCES:
patent: 4127900 (1978-11-01), Raffel et al.
H. S. Lee, "MNOS Varactor Bootstrap Memory Cell", IBM Technical Disclosure Bulletin, vol. 17, No. 11, Apr. 1975, p. 3214.

Affiliated with

Also associated with

Rating

Nonvolatile JRAM cell using nonvolatile capacitance for informat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile JRAM cell using nonvolatile capacitance for informat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile JRAM cell using nonvolatile capacitance for informat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1579856